Chips are the quintessence of human technology and are often called the crown jewels of modern industry.
The basic components of a chip are transistors. While the basic operating principle of a transistor isn't complex, packing tens of billions of them into an area as small as a fingernail makes this a complex undertaking. It's even considered the most complex engineering feat ever undertaken.
Over the next few days, Xiaozao will be introducing the chip manufacturing process in a series of articles.
Today, I'll focus on wafer manufacturing.
█ Main Stages and Division of Labor
Before introducing wafers, Xiaozao will first provide some background on chip manufacturing.
Chip manufacturing involves hundreds of steps, which can be categorized into four main stages: chip design, wafer preparation, chip manufacturing (front-end), and packaging and testing (back-end).
How are wafers manufactured?
We often hear terms like fabless, foundry, and integrated device manufacturing (IDM). These terms are closely related to the division of labor in the chip industry.
Generally speaking, some companies in the industry focus solely on chip design. Companies that don't manufacture, package, or test chips are considered fabless companies, such as Qualcomm, Nvidia, MediaTek, and (formerly) Huawei.
Some companies specialize in chip production and don't produce their own branded chips. These companies are considered foundries, or wafer foundries.
The most famous foundry is, of course, TSMC in Taiwan. Semiconductor Manufacturing International Corporation (SMIC), United Microelectronics Corporation (UMC), and Huahong Group are also foundries.
TSMC
Chip manufacturing is even more challenging than chip design. Many companies in China have the ability to design advanced process chips, but they can't find a foundry to manufacture them. Therefore, the so-called "bottleneck" refers to the chip manufacturing process.
The chips produced by a foundry are generally called bare dies. Bare dies cannot be used directly and require packaging, testing, and other steps. Manufacturers that specialize in packaging and testing are called OSATs (Outsourced Semiconductor Assembly and Test).
Of course, some wafer fabs have their own packaging and testing facilities, but these are generally not as flexible and easy to use as OSATs. Well-known OSATs include Advanced Semiconductor Manufacturing (ASE), Changjiang Electronics Technology, United Technologies (UTAC), and Amkor.
Finally, there are IDMs.
IDM stands for Integrated Device Manufacturer. Some companies offer chip design, wafer fabrication, and packaging and testing, encompassing an end-to-end approach. These companies are called IDMs.
There are not many companies globally with this capability, including Intel, Samsung, Texas Instruments, and STMicroelectronics.
IDMs may seem impressive, capable of doing everything. However, the chip industry is vast, and refined division of labor is the prevailing trend. The fabless + foundry model, with its specialized expertise, offers advantages in terms of professionalism, efficiency, and profitability.
AMD was once an IDM, but later shifted gears to the asset-light fabless model. After its wafer fab was spun off, it transformed into GlobalFoundries, one of the world's top five wafer foundries.
█ Wafer Preparation
Okay, let's look at the specific manufacturing process.
First, let's start with the most basic wafer preparation.
This is the wafer.
We often say that chips are made of sand. Actually, this is mainly because sand contains a large amount of silicon (Si).
Silicon is the second most abundant element in the Earth's crust, second only to oxygen.
Sand contains silicon, but its purity is very low, and it is in the form of silicon dioxide (SiO2). We can't just pick up a handful of sand and extract silicon. Typically, quartz sand ore with a relatively high silicon content is used.
High-purity quartz sand ore
The first step is deoxidation and purification.
Quartz sand is placed in a furnace and heated to temperatures exceeding 1400°C (silicon's melting point is 1410°C). It then reacts with a carbon source to produce high-purity (over 98%) metallurgical-grade industrial silicon (MG-Si).
Metallurgical-grade industrial silicon
Subsequently, it is further purified through chlorination and distillation processes to obtain even higher-purity silicon.
Silicon is used not only in semiconductor chip manufacturing but also in the photovoltaic industry (solar power generation).
In the photovoltaic industry, the required purity for silicon is 99.9999% to 99.9999999%, representing 4 to 6 nines. This is called (SG-Si).
Photovoltaic panels
In the semiconductor chip industry, the purity requirement for silicon is even more extreme, reaching 99.9999999% to 99.999999999%, representing 9 to 11 nines. This type of silicon used in semiconductor manufacturing is known as electronic-grade silicon (EG-Si). On average, only one impurity atom is allowed per million silicon atoms.
The second step is to pull a single crystal silicon (ingot).
This purified silicon is polycrystalline silicon. Next, it needs to be converted into single crystal silicon.
In my previous brief introduction to the history of semiconductor development, Xiaozaojun explained the differences between single crystal silicon and polycrystalline silicon.
Simply put, single crystal silicon has a perfect crystal structure and excellent performance. Polycrystalline silicon has large, irregular grains, many defects, and relatively poor performance across the board. Therefore, high-end products like chips are essentially made of single crystal silicon. Photovoltaics can use polycrystalline silicon.
The current mainstream method for converting polycrystalline silicon into single crystal silicon is the Czochralski method (also known as the Czochralski method).
First, high-purity polycrystalline silicon is heated and melted to form liquid silicon.
A large-scale single crystal melting furnace.
Then, a thin strip of single crystal silicon is inserted into the silicon solution as a seed (also called a silicon seed crystal). Next, the puller slowly rotates upward. The pulled silicon solution solidifies into solid silicon pillars due to the decreasing temperature gradient.
Led by the silicon seed, the silicon atoms leaving the liquid surface solidify in a "line," forming neatly arranged single-crystal silicon pillars.
(Note that the pulling speed varies. Initially, a solid silicon pillar of approximately 10 cm is pulled at a speed of 6 mm/minute. This is primarily because the initial crystal formation is subject to thermal shock, making the crystal phase unstable and prone to crystal defects. After a length of 10 cm, the speed can be slowed down and the puller can be pulled slowly.)
The pulling speed and temperature control significantly affect the quality of the crystal pillar. The larger the silicon pillar, the higher the speed and temperature requirements.
Finally, a cylindrical silicon pillar is pulled, typically with a diameter of 30 cm and a length of approximately 1-1.5 meters. This silicon column is the ingot, also called a silicon ingot (haha, it sounds similar to "turtle butt" and "regulation").
The third step is wafer slicing.
The pulled silicon ingot is trimmed of its head and tail, then sliced into thin slices (silicon wafers) of a specific thickness.
The current mainstream slicing method uses a multi-wire saw with diamond wire. This machine uses a steel wire with diamond particles fixed to it to cut the silicon segment in multiple sections. This method is highly efficient and minimizes losses.
Diamond Wire Saw
Slicing is sometimes also done with an internal circular saw. An internal circular saw uses a thin diamond-coated blade on the inner circle, which is rotated to slice the ingot. Internal circular saws offer relatively high cutting accuracy and speed, making them suitable for slicing high-quality wafers.
How is it manufactured?
Internal Circular Saw
Since silicon wafers are very fragile, the slicing process requires extreme care, with strict temperature and vibration control. A water-based or oil-based cutting fluid is required for cooling and lubrication, as well as to remove debris generated by the cutting process.
The fourth step is chamfering, grinding, and polishing.
The cut silicon wafer is called a "bare die," or "raw wafer"—an unprocessed product.
The surface of the bare die is very rough and contains residual cutting fluid and debris. Therefore, chamfering, grinding, polishing, and cleaning are required to complete the post-cutting process and ultimately produce a mirror-smooth "finished wafer."
Chamfering involves using a chamfering machine to round the right-angled edges of the silicon wafer. This is because high-purity silicon is a highly brittle material, and this process reduces the risk of edge cracking.
Lapping is a rough grinding process to achieve a flat and parallel wafer surface and minimize mechanical defects.
After lapping, the wafer is etched in a mixture of nitriding acid and acetic acid to remove any microcracks or damage. After etching, the wafer passes through a series of high-purity RO/DI water baths to ensure surface cleanliness.
Wafers are polished through a series of chemical and mechanical polishing processes, known as CMP (Chemical Mechanical Polish).
During the chemical reaction phase, the chemical components in the polishing slurry react with the wafer material being processed, forming easily removable compounds or softening the surface.
During the mechanical grinding phase, the polishing pad and abrasive particles in the polishing slurry mechanically abrade the wafer material, removing the compounds formed during the chemical reaction phase and other surface impurities.
In the CMP process, the wafer to be polished is first secured to the polishing machine's wafer holder. Next, the polishing slurry is evenly distributed between the wafer and the polishing pad. The polishing machine then polishes the wafer by applying appropriate pressure and rotational speed.
CMP is a common process in chip manufacturing (and will be used again later). Its core goal is to achieve global planarization, eliminating surface variations (such as unevenness in metal and dielectric layers) with nanometer-level precision, preparing the wafer for subsequent processes such as photolithography.
Step 5: Cleaning.
After polishing, the wafers need to be thoroughly cleaned to remove any residual polishing fluid and abrasive particles.
Cleaning typically involves multiple steps, including acid, alkaline, and ultrapure water rinses. Each step must be performed in a cleanroom environment to prevent any new impurities from adhering to the wafer surface.
Step 6: Inspection and Sorting.
The wafers obtained after polishing are also called polished wafers.
Finally, the polishing results are rigorously inspected using an optical microscope or other inspection equipment to ensure that the wafer's surface flatness, material removal, thickness, surface defects, and other indicators meet the expected requirements.
Wafers that pass the inspection will proceed to the next process. Those that fail the inspection will be reworked or discarded.
Note: In actual production, wafer edges are cut with flat corners or notches to facilitate positioning and crystal orientation in subsequent processing steps. In addition, serial number labels are stamped on the reverse edge of the wafer to facilitate material tracking.
Frequently Asked Questions About Wafers
Okay, the wafers have been prepared. Next, let's answer a few frequently asked questions about wafers.
Question 1: What size are wafers?
The finished wafers obtained after processing come in a variety of sizes, such as 2-inch (50mm), 3-inch (75mm), 4-inch (100mm), 5-inch (125mm), 6-inch (150mm), 8-inch (200mm), and 12-inch (300mm).
Small-Size Wafers
Of these, 8-inch and 12-inch sizes are the most common.
Wafer thickness must strictly adhere to SEMI specifications and other standards. For example, the thickness of a 12-inch wafer is typically controlled within a range of 775μm ± 20μm (micrometers), or approximately 0.775 mm.
The larger the wafer size, the more chips can be produced per wafer, and the lower the unit chip cost.
Take 8-inch and 12-inch silicon wafers as an example. Under the same process conditions, a 12-inch wafer has more than twice the usable area of an 8-inch wafer, and its usability (a measure of the number of chips that can be produced per wafer) is approximately 2.5 times that of an 8-inch wafer.
However, the larger the wafer, the more difficult it is to manufacture, requiring more production technology, equipment, materials, and processes.
A 12-inch wafer offers a relatively good balance between profitability and difficulty.
Question 2: Why are wafers round?
First, as mentioned earlier, the single crystal is pulled out as a cylinder, so after cutting, it becomes a disc.
Second, cylindrical single crystal silicon ingots are easier to transport, minimizing material loss due to bumps and collisions.
Third, round wafers facilitate uniform heating and cooling during the manufacturing process, reducing thermal stress and improving crystal quality.
Fourth, a round wafer also facilitates subsequent chip processing.
Fifth, it offers advantages in area utilization. As we'll discuss later, many chips are manufactured on a wafer. The chips are indeed square. Logically, it seems that square wafers are more suitable for square chips (there's no waste at the edges).
How are wafers manufactured?
But in reality, even when they're square, some edges remain unusable. Calculations show that rounded edges result in less waste than square ones.
Question 3: Are wafers necessarily made of silicon?
Not necessarily.
Not only silicon can be used to make wafers. Currently, semiconductor materials have reached the fourth generation.
First-generation semiconductor materials are represented by Si (silicon) and Ge (germanium). Second-generation semiconductor materials are represented by GaAs (gallium arsenide) and InP (indium phosphide). Third-generation semiconductor materials are represented by GaN (gallium nitride) and SiC (silicon carbide). Fourth-generation semiconductor materials are represented by aluminum nitride (AlN), gallium oxide (Ga2O3), and diamond (C).
However, over 90% of chips currently use semiconductor wafers as substrates. This is because silicon wafers offer excellent semiconductor properties, abundant reserves, and mature manufacturing processes.
